1. Field of the Invention
The invention relates to a semiconductor storage device which operates at low voltage and an operation method thereof, and particularly relates to a semiconductor storage device having a static memory cell formed by transistors as a memory cell, that is, a circuit of a static memory (Static Random Access Memory: hereinafter, abbreviated as SRAM) which is suitable for low voltage.
2. Description of the Related Art
The SRAM is widely used as a general-purpose memory-logic integrated memory. Particularly, the SPAM including p-channel MOS (PMOS) transistors PT1, PT2 as load transistors, n-channel MOS (NMOS) transistors NT1, NT2 as driver transistors and NMOS transistors NT3, NT4 as access transistors (hereafter, abbreviated as 6Tr-SRAM) has high affinity for a logic process and is widely used as a memory which can operate at high speed.
However, as miniaturization of a semiconductor integrated circuit advances as well as the cell area of the SRAM is reduced in recent years, there is a problem of effects of characteristic variations of MOS transistors with respect to operational stability of the SRAM.
As a method of suppressing power consumption of the semiconductor integrated circuit, there is a method in which the SRAM is driven at high voltage at the time of high-speed operation and the SRAM is driven at low voltage at the time of low-speed operation or at the time of standby.
In this case, operation at lower voltage than a power supply voltage (Vdd) to be supplied to the SRAM is necessary, therefore, margin of operational stability is reduced, which further increases effects of characteristic variations of MOS transistors.
FIG. 2 is a graph showing power supply voltage dependence of Static Noise Margin (hereinafter, abbreviated as SNM) indicating data holding stability of the 6Tr-SRAM.
As can be seen from FIG. 2, in the 6Tr-SRAM, as the power supply voltage is reduced, the SNM is reduced.
When the SNM is reduced, the data holding of the SRAM becomes unstable, and particularly, problems such that data is improperly written at the time of reading operation occur.
FIG. 3 is a graph showing the SNM of the 6Tr-SRAM whose character variations of MOS transistors are large.
As shown in FIG. 3, curves of output characteristics of right-and-left nodes are imbalance and distorted due to variations of MOS transistors, which reduces the SNM.
As a method of reducing the effect of characteristic variations of MOS transistors, there is a method of using a 5Tr-SRAM (refer to U.S. Pat. No. 5,831,896 (Patent Document 1)) shown in FIG. 4.
The SRAM usually holds data at a flip-flop portion formed by a pair of inverters. A data holding characteristic at the flip-flop portion will be the one in which normal inverter curves are combined as shown in FIG. 5.
The 6Tr-SRAM reads data held in the flip-flop portion by connecting output portions (a first node ND1 and second node ND2) of first and second inverters INV1, INV 2 to a first bit line BL1 and a second bit line BL2 through first and second NMOS transistors NT3, NT4 for data access and by allowing the NMOS transistors NT3, NT4 for data access to be an ON state through a word line WL1.